| 摘要 |
PURPOSE:To prevent reduction of allowance of operation caused by fluctuation of power source, grounding level and substrate potential by making a writing system, especially a data in buffer operatable state after termination of operation of a sense amplifier and generation of sufficient differential potential in a pair of bit lines. CONSTITUTION:In a memory provided with a clock generator for controlling a row system, a generator that receives synchronizing signals from a column system and synchronizing signals and row address strobe signals from the column system and generates controlling clock of write enable system, the write system clock generator 5 is activated on receiving a signal S2 generated after forming sufficient differential potential between bit lines after termination of amplification of signals by a sense amplifier 10 out of signals of the column system clock generator 1. Thereby, more stable writing operation can be made without narrowing operational allowance of a data in buffer 6 due to fluctuation of power source, grounding level and substrate potential caused by discharging of many bit lines at the time of operation of the sense amplifier.
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