| 摘要 |
PURPOSE:To obtain a memory device of high speed and low power consumption by providing a group selecting line to a row direction division group of memories arranged in matrixlike form, a column decoder, a front word line connected to decoder output and a divided word line activated by signals of the group selecting line and front-end word line to the middle of the direction of group arrangement. CONSTITUTION:To select a cell in a cell in a memory cell group 1a, row address information of the group 1a to be accessed is interpreted by a row decoder 4 provided in the middle of the direction of arrangement of the memory cell group, and one of front word lines is activated. When a selection signal is applied to a group selecting line 14a, an AND gate is opened, and a word line 3a is activated, and current flows in only to rows in the group 1a from a bit line. The front word line 15 is made of material of low resistance to enable high speed access, and cell selection is made separately in two stages of the front word line and word line. Thus, the number of columns of the row decoder is reduced, and power consumption can also be lowered. |
