发明名称 Logic circuit.
摘要 <p>A logic circuit includes an inverter circuit including a first enhancement type field effect transistor (21) having a gate connected to an input and a first depletion type transistor (22) having a gate and a source which are directly connected together and to a drain of the first enhancement type field effect transistor (21); a source follower circuit including a second enhancement type field effect transistor (23) having a gate which is connected to a connecting point of the first enhancement type field effect transistor (21) and the first depletion type field effect transistor (22) and a second depletion type field effect transistor (25) having a gate and a source which are directly connected to each other and a drain which is connected to a source of the second depletion type field effect transistor (23); a circuit which supplies power to the drains of the first depletion type field effect transistor (22) and of the second enhancement type field effect transistor (25) and to the sources of the first enhancement type field effect transistor (21) and of the second depletion type field effect transistor (23); and, an output is formed at the connecting point (26) of the second enhancement type field effect transistor (23) and the second depletion type field effect transistor (25) which form the source follower circuit. </p>
申请公布号 EP0226678(A1) 申请公布日期 1987.07.01
申请号 EP19850309492 申请日期 1985.12.24
申请人 FUJITSU LIMITED 发明人 TAKAO, HISOKA;SATO, TOSHIRO;SAITO, SEIICHI;HAYASHI, TOSHINARI
分类号 H03K19/0944;H03K19/0952;(IPC1-7):H03K19/094 主分类号 H03K19/0944
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