| 摘要 |
<p>PURPOSE:To process collectively the delay amounts of each control circuit by providing a working state register, which sets the delay amount to a prescribed clock for each clock signal applied to each device, and an adjusting circuit which selects a delay amount in compliance with said delay amount. CONSTITUTION:A working state register 1 sets the delay amount to a subject clock via a maintenance processor SVP. The set clock given from the SVP and the address of the register 1 sent via a decoder 2 are turned into a set signal via an AND circuit 3. Then the delay amount given from the SVP is set by a write data bus and confirmed from a read data bus. The contents of this delay amount are decoded by a decoder 4 and given to series circuits 51-54 which select various delay amounts 61-64 respectively. Then a fed clock/stop signal is delayed by an amount equal to the delay amount of a selected circuit. While the clock/ stop signal is delivered through a circuit which is not selected.</p> |
