| 摘要 |
PURPOSE:To contrive the reduction of price and the improvement in performances of a semiconductor device by narrowing a width of an element isolation region so as to increase an areal efficiency in a semiconductor substrate and reducing a parasitic inductance and facilitating handling of chips. CONSTITUTION:On a GaAs substrate 101, a source electrode 102s, a gate electrode 102g, and a drain electrode 102d are formed. In an element isolation region 11, a groove 12 having the width which reaches the source electrode 102s is formed and in that groove, an insulating layer 13 having a resistance to acids and bases is formed. Next, a metallic layer 14 which covers the insulating layer 13 and connects the adjacent source electrodes 102s is formed and the substrate is turned over to be fixed to a base 107 by use of a soluble resin layer 106. The insulating layer 13 is exposed by polishing and a groove 15 is formed in the part which is in contact with the insulating layer 13. Furthermore, the substrate is etched to expose the source electrode 102sa. Subsequently, the source electrode exposed part 102sa is plated with gold to form a filling layer 16. On this filling layer 16 and the substrate 101, a metallic layer 17 is formed and further a gold plated layer 18 is formed. Then, the insulating layer 13 and the source electrode connecting metallic layer 14 are removed and a chip is taken off from the base 107.
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