| 摘要 |
<p>A set of contiguous address bands for a memory comprising a series of memory modules (11) is provided by a control system (16, 24) which allocates a start address to the first of the memory modules in the series and then allocates a start address in turn to each successive one of the remainder of the memory modules in response to signals indicative of the start address and capacity of the previous memory module in the series. Each memory module includes a device (12) to indicate its capacity and the control system includes an adder (16) for adding a memory module (11) start address (on line 18) to the capacity (on line 14) of that memory module (11) to produce (on line 20) the start address for the next module.
<??>Each module may include an address comparing device (24) responsive to the capacity of that module and the start address of that module to determine whether an input address is within the allocated address band for that module.
<??>In alternative arrangements (Figs. 3 and 4), the adders and address comparing devices may be located in a central control system (100; 200) connected to the memory modules. </p> |
