| 摘要 |
PURPOSE:To attain high speed and low noise by adopting the constitution of 3-stage of changeover for a gate potential of an N-MOS transistor (TR) in an output circuit of complementary operation. CONSTITUTION:An N-MOS TR 3 is turned from ON to OFF and an N-MOS TR 5 is turned from OFF to ON in the process that a data potential inputted from a terminal 16 changes from an L level to an H level, a gate potential of an N-MOS TR 4 goes to a middle potential and the N-MOS TR 4 is conductive, its conductance is not maximized and since the discharge time constant of a load capacitance 14 is large, an output terminal voltage V0 falls down gradually. Then a NAND 13 and inverters 9, 10 act like a delay circuit, a potential at a point B reaches an L level with a delay, then a P-MOS TR 2 is turned on, the potential at a point A rises to an H level from an intermediate potential, the conductance of the N-MOS 4 is maximized and the output terminal voltage V0 decreases quickly. Since the decrease in the voltage V0 is a decrease from the intermediate output voltage, the effect onto a GND level is suppressed and no malfunction is caused even when the entire operation is quickened.
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