Addressing circuit for a matrix display incorporating shift registers formed from static memories and addressing process using such a circuit

摘要

Addressing circuit for a matrix display having shift registers formed by static memories and process for addressing with such a circuit. For a display with p columns, the circuit comprises p register points formed by static memories (Mi), a first series of switches (C1) placed in front of the register points Mk-1, k being an even number between 1 and p, a second series of switches (C2) placed in front of the register points Mk and a transfer clock (13) producing a first signal ( phi 1) controlling the first series of switches, in order to ensure the loading of a "1" signal into the register point (M1) and the transfer of the content of register point Mk to register point Mk+1, and a second signal ( phi 2) controlling the second series of switches for ensuring the transfer of the content of register point Mk-1 to register point Mk.