发明名称 |
DIGITAL PHASE-LOCKING LOOP CIRCUIT |
摘要 |
<p>The digital phase-locked loop circuit extracts the clock signal from a serial flow of coded data by operating so as to determine the phase of the received signal and comparing this phase with that of a locally-generated signal. The error signal obtained from the comparison is digitally filtered and used to correct the phase of local signal. The error with respect to the signal extracted from a prior data stream is stored and used to effect corrections even in the absence of the data flow at the input or in presence of long zero sequences.</p> |
申请公布号 |
JPS62145924(A) |
申请公布日期 |
1987.06.30 |
申请号 |
JP19860296856 |
申请日期 |
1986.12.15 |
申请人 |
CSELT SPA (CENT STUD E LAB TELECOMUN) |
发明人 |
KARURO MOGABUERO BURUNO;RENATO AMUBUROSHIO |
分类号 |
H03L7/06;H04L7/033 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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