| 摘要 |
<p>PURPOSE:To detect asynchronism of clocks correctly even if input clocks include jitter, by inputting the output of a logic circuit, which outputs a signal which is made wider by a certain range before and after a stable point of the clock synchronous state, to a phase comparator as the data input. CONSTITUTION:An input clock 9 of a gate circuit 100 and write clocks 11-5 and 11-8 are inputted to a gate circuit 108, and the circuit 108 outputs a signal 17(b-1). Input signals (a-1), (a-2), and (b-2) of the first phase comparing circuit are a write clock 11-1 and a read clock 13-1, and signals (b-1) and (b-2) are inputted to the second phase comparing circuit 105 consisting of a flip flop to compare phases, and the signal (b-1) is read with the signal (b-2); and therefore, logical '0' is always outputted even if the phase difference between the first clock 9 and the second clock 12 is fluctuated relatively to +4--3.5 bits, and clocks asynchronism is detected correctly even for 2-fold conventional phase fluctuation.</p> |
