发明名称 SEMICONDUCTOR MEMORY
摘要 PURPOSE:To access a column address independently of the operation of a sense amplifier at refresh timing by amplifying and holding data based on a sense amplifier by a holding circuit having the same constitution as the sense amplifier. CONSTITUTION:A memory cell 9 and a dummy cell 10 selected respectively by a word line W and a dummy word line D' and respectively connected to bit lines BL, the inverse of LB to start the sensing operation of the sense amplifier 6. Then, FETs 16, 17 are turned on by a timing clock and a potential difference between both the bit lines which is amplified by the amplifier 6 is more rapidly amplified and held by the holding circuit 13 having the same struction as the amplifier 6. Then, FETs 11, 12 are turned off by a timing clock, and under the state that the bit lines BL, the inverse of BL are separated from nodes N2, the inverse of N2, an output of the amplifier 6 is held in the circuit 13. Even if the sense amplifier is driven at the refresh timing, an column address can be accessed without inhibiting the column address independently of the driving of the sense amplifier, so that highly sensitive and rapid access can be attained.
申请公布号 JPS62146491(A) 申请公布日期 1987.06.30
申请号 JP19850288330 申请日期 1985.12.20
申请人 SANYO ELECTRIC CO LTD 发明人 WADA TOSHIO;ABE NORITOSHI
分类号 G11C11/401;G11C11/34;G11C11/406;G11C11/409 主分类号 G11C11/401
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