| 摘要 |
PURPOSE:To detect clock pulse disconnection even in a circuit assembled in a gate arrays by adopting the constitution that a clock pulse disconnection detecting circuit is constituted by logic elements only. CONSTITUTION:When a clock pulse is inputted continuously to an input terminal IN, the result of detection of a D flip-flop 4 outputs a high level to an output terminal OUT. When the clock pulse input is interrupted, the output of the oscillator 1 goes to a high state, after a 1/2 frequency-divider 2 and an RS flip-flop 3 are reset, the output of the oscillator 1 goes to a low state, since the output of the 1/2 frequency-divider 2 remains at a low level and is not inverted, then the D flip-flop 4 reads the low level and a low level is outputted to the check result output terminal OUT. While the oscillator 1 outputs a low level, when >1 clock pulse is inputted, it is detected. |
