| 摘要 |
<p>PURPOSE:To secure the reset of a bit line potential, and to reduce an access time by outputting the second clock ATC to the second clock generation circuit by a control circuit, and lengthening the pulse width of a reset signal, when a chip non-selection signal having the pulse width shorter than a time required for the reset of the bit line potential is inputted to a control circuit. CONSTITUTION:A CS buffer 4 inputs the chip non-selection signal, and performs the inversion and the delay of the signal appropriately. An address signal ADD is inputted to another input of a NOR gate 21. An address buffer 23 is connected to an ATC generation circuit 2 and a decoder 24, furthermore, a memory cell array 25 is connected to the decoder 24. A clock CTC from a CTC generation circuit 1 and a clock ATC from the ATC generation circuit 2 are inputted to a gate circuit 3, and the gate circuit 3 outputs a reset signal (phi) to reset the potential of a pair of bit lines connected to each memory cell within the memory cell array 25 at the same potential based on two kinds of clocks, the CTC and the ATC.</p> |
