SYSTEM RESET CONTROL SYSTEM

摘要

PURPOSE:To prevent the memory access from being intermitted forcibly by issuing a bus enable permission to a bus using request immediately when no master during access exists in a bus arbitration circuit. CONSTITUTION:When an RSTSW signals is inputted to a reset control circuit 1 after a reset switch is depressed, the reset control circuit 1 uses a bus request signal BR7 to request a bus to a bus arbitration circuit 3. When the bus request circuit 3, based on the request, decides the provision of the next bus cycle, it is informed to the reset control circuit 1 by using a bus enable permission signal BG7. When the reset control circuit 1 receives the bus using enable signal BG7, an access signal AS is negated, and when a BGACK is negated, a bus using acknowledge signal BGACK and a reset signal RESET are outputted immediately and each section is reset.