| 摘要 |
PURPOSE:To prevent the delay in access by applying control from a control circuit to open a gate when the pulse width of a chip non-selection signal is shorter than a prescribed time. CONSTITUTION:A clock ATC in an ATC generation circuit 5 is generated with a delay when an address signal ADD changes by the transmission of a NOR gate 2 and an address buffer 11, and since there is a timing deviation with the generation of the clock CTC, when a signal at a point (d) in figure is at a low level, that is, when the pulse width of a chip non-selection signal CS is short, the clocks ATC and CTC are added and the pulse width of a reset signal phi is prolonged more than the clock CTC. When the signal at a point (d) is at a low level, the address signal ADD is sent to an internal circuit 1 via the NOR gate 2.
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