发明名称 BRANCH TRACE CONTROL SYSTEM
摘要 PURPOSE:To reduce the quantity of hardware by checking whether a branching source address and a branched address are included within previously set upper and lower limit addresses by an existing arithmetic circuit. CONSTITUTION:The upper and lower limit addressed of the branching source address and the branched address are stored in an LS area 51 of a main storage in addition to a pointer and a byte counter. When a branching condition is formed and branching is executed, the branching source address and the branched address are set up on one input of the arithmetic circuit (ALU) 1 and the upper and lower limit addresses stored in the specific area are extracted and set up to the other input to execute four operations. A carry/output zero detecting circuit 9 inputs a carry output to be '1' when the calculated result of the ALU 1 is a negative value and a zero output to be '1' when the calculated result is zero to test the input.
申请公布号 JPS62143143(A) 申请公布日期 1987.06.26
申请号 JP19850283711 申请日期 1985.12.17
申请人 FUJITSU LTD 发明人 NISHIOKA JUNJI;SATO MASAO
分类号 G06F11/28 主分类号 G06F11/28
代理机构 代理人
主权项
地址