| 摘要 |
PURPOSE:To improve the using efficiency of a system by providing a means for executing refresh operation of a DRAM, a means for transferring data, a means for releasing an address bus releasing request, and a means for inhibiting the output of a signal indicating the release of an address bus and data. CONSTITUTION:A refresh controller 6 receiving a signal HOLD ACK outputs a refresh address to the DRAM 3 through an address bus 33 and outputs a refresh control signal to the DRAM 3 through a control signal line 41. Thus, the refresh controller 6 executes the refresh operation of the DRAM 3. After completing the refresh operation, the refresh controller 6 releases a signal HOLD REQ. so that a CPU 1 inhibits the signal HOLD ACK and manages the address bus and the control bus to execute the processing operation. Consequently, the system can be highly efficiently utilized.
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