| 摘要 |
PURPOSE:To attain efficient parallel operation of a multi-bus by executing another bus cycle again after the end of a certain bus cycle to attain a cycle steel operation for the multi-bus including a DMA cycle. CONSTITUTION:At the end of data transfer of one cycle from a source memory to a destination memory, a destination memory response signal 27 is inputted to terminals B of NAND circuits 23, 24, a bus is opened and a bus cycle for another channel requesting DMA service is executed. At the end of the other bus cycle, the initial bus cycle is executed again. The cycle steel operation for the multi-bus is executed by repeating said operation. consequently, data transfer including other channels can be uniformly executed and the efficient parallel operation of the multi-bus can be executed.
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