| 摘要 |
PURPOSE:To detect the malfunction of a system and to reset the whole system by providing one malfunction detecting timer and one malfunction detecting circuit. CONSTITUTION:A CPU managing circuit 5 constitutes a counter of two stages of T-type flip flops 6 to determine a CPU 1 to be retriggered. The circuit 5 selects one of retriggers I-IV of the CPUs I-IV to be required for a malfunction detecting timer 2 by an AND gate and retriggers the timer 2 by an OR gate 8. Namely, the circuit 5 selects retrigger pulses generated from respective CPUs I-IV successively at retrigger pulses for the timer 2. When a retrigger pulse is not outputted from the CPU 1 (namely, malfunction), the timer 2 overflows and the whole system is reset by an overflow detecting circuit 4, so that the system and the CPU 1 can be restarted.
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