| 摘要 |
PURPOSE:To prevent data in a dynamic RAM from being damaged at the time of data processing based upon a direct memory access (DMA) controller by inputting an address strobe signal from the DMA controller. CONSTITUTION:When the access of the dynamic RAM 15 is to be controlled by the DMA controller 13, a CPU 11 outputs signals RD, WR and IO/M and transfers control to the DMA controller 13. Consequently, the DMA controller 13 supplies an address signal required for an address latch 14 and supplies an address storbe signal ADSTB to an interface 20. A RAM controller 18 and the interface 20 are chip-selected by an address decoder 17 and a start signal RASIN is supplied from the interface 20 to the RAM controller 18 to start the RAM controller 18. Consequently, the dynamic RAM 15 is started and data read/write from/in the dynamic RAM 15 is controlled by the DMA controller 13 in addition to data refresh.
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