| 摘要 |
PURPOSE:To attain a high-speed serial output from an optional bit by providing a latch circuit, a shift register of the constitution forming a selection signal of a switch MOSFET and feeding back the final stage output to the 1st stage circuit, and a mean amplifier amplifying the signal. CONSTITUTION:A signal of a memory array is transferred to a latch circuit FF via a switch circuit SW, and signals D0, the inverse of D0-Dn, the inverse of Dn stored therein are transferred to common data lines CD, the inverse of CD via switch MOSFETs Q1, Q2-Q3, Q4 controlled by a selection signal formed by the shift register SR. In this case, the main amplifier MA is provided to the 1st stage circuit of the shift register SR, then the signals Dn, the inverse of Dn transferred by the selection signal of the final stage circuit have the largest signal propagation delay time and the maximum transfer time of the selection signal, while the signals D0, the inverse of D0 transferred by the selection signal of the 1st stage circuit are sent to the amplifier MA fastest. Thus, the frequency of the shift clock signal phi is set while taking the time into account to attain efficient high-speed read.
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