发明名称 CLOCK SIGNAL PERIOD IDENTIFICATION CIRCUIT
摘要 PURPOSE:To control such as starting, stopping, initializing etc. of all or a part of circuits constituting the circuit without requiring exclusive wiring by connecting a smoothing circuit different in speed of response between the case where voltage applied to an input terminal rose steeply and the case where voltage dropped steeply to an edge trigger type memory circuit. CONSTITUTION:A gate electrode is connected to a clock signal line 1, and one of main electrodes is connected to a power source potential end 3 and another main electrode is connected to the input end 4a of an edge trigger type memory circuit 4 and at the same time, connected to an end of a resistor 5 and to an end of a capacitor 6. Other terminals of the resistor 5 and capacitor 6 are connected to grounding potential end 7, and a clock signal line 1 is connected to the trigger input end 4b of the edge trigger type memory circuit 4. The output end 4c of the edge trigger type memory circuit 4 is connected to an output signal line 8 that transmits signals to circuits that are objects to be controlled.
申请公布号 JPS62142415(A) 申请公布日期 1987.06.25
申请号 JP19850284692 申请日期 1985.12.17
申请人 MITSUBISHI ELECTRIC CORP 发明人 TAMURA TOSHIYUKI;KOMORI NOBUFUMI
分类号 H03K5/19;H03K5/153 主分类号 H03K5/19
代理机构 代理人
主权项
地址