| 摘要 |
PURPOSE:To prevent the malfunction of an address buffer by inhibiting an address signal from changing while a current is changing due to the transitional action of an output buffer and maintaining the previous address signal. CONSTITUTION:The titled device has an ouptut change detection circuit 8 detecting a change in an output when stored data is read out, and an address change inhibiting circuit 9 receiving the output of said output change detection circuit 8. Pulse width is set according to the values of capacitances C1, C2, C3 and C4 so that said width can be the same as the time showing a transitional action by receiving a change in the output signal of a sense amplifier 6, and therefore the output change detection circuit 8 outputs a signal CL at a low during said period and its inverse signal CL which becomes high while an instan taneous voltage drops appears. Receiving the output signal CL and the inverse of CL from the output change detection circuit, the address change inhibition circuit 9 does not operate a clock inverter 18. While the inverse signal CL is at a high level, the gate of a clock inverter 16 is opened. Therefore, the address signal is separated from the row and column decoders and the address buffer, and data held by an inverter 17 and the clock inverter 18 is transmitted to the row and column decoders.
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