| 摘要 |
PURPOSE:To reduce the occupied area of a memory cell by constructing a DRAM device of the following two transistors: the 1st transistor for writing and selecting and the 2nd transistor for reading, selecting and amplifying stored contents. CONSTITUTION:Such an MOS structure that has an upper gate electrode UG as the 2nd gate G22 and a lower gate electrode DG as the 1st gate G21 in a channel forming area CH2 between a source S2, which is formed on a substrate 1 as a thin film and a drain D2 through insulating films U1 and D1, is supplied to the 2nd transistor T2, and a read selection line RS and a capacity C are connected to the gate electrode DG and the gate electrode UG. In terms of R(0) reading '0', the write selection line WS is at a zero potential to disconnect the 1st transistor T1, and the 2nd transistor T2 is conductive from the zero potential of the selection line RS and the charge of the capacity C, thereby executing read selection and amplification. Thus the occupied area can be reduced by a space for one transistor, and a capacity capable of controlling a gate sufficies accordingly. |
