发明名称 PATTERN SPLIT EFFECT GENERATING SYSTEM
摘要 PURPOSE:To simplify the circuit constitution in comparison with the pattern split effect at a readout side address being a nonlinear address by applying the pattern split effect at the write side being a linear address. CONSTITUTION:The pattern split key generation circuit 3 generates a split key signal representing the region subjected to pattern split in interlocking with a write address. A key signal superimposing circuit 1 superimposes a split key signal fro the pattern split key generating circuit 3. Then the video signal is written in a picture memory 2 based on a write address attended with the pattern split effect from a write address generating circuit 4 and read by a read address generating circuit 5. The video signal read by the read address generating circuit 5 is subject to pattern split already and separated into the video signal and the key signal by a key signal split circuit 6 of the next stage.
申请公布号 JPS62142473(A) 申请公布日期 1987.06.25
申请号 JP19850283944 申请日期 1985.12.17
申请人 NEC CORP 发明人 HIRAYAMA KEIICHI
分类号 H04N5/265 主分类号 H04N5/265
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