| 摘要 |
PURPOSE:To simplify the constitution of the titled circuit, also to execute at a high speed decoding to an NRZ code from a CMI code, and to execute a processing by a single clock signal, by decoding a CMI code signal to the data signal of the NRZ code, the CMI rule violating signal of a data '0', and the CMI rule violating signal of a data '1', by the single clock signal. CONSTITUTION:An AND gate 10 outputs a signal (i) only when a data signal (e) is '1'. That is to say, it is a signal for outputting '1', when the violation of a data '1' of the CMI rule is detected, and this signal (j) is outputted to a terminal 15 as the CMI rule violating signal of the data '1'. Also, an AND gate 11 outputs '1', when both a Q output (c) of a flip-flop 4 and the inverse of Q output of a flip-flop 5 are '1', namely, when the first half bit of a time slot of a CMI code signal (a) is '1' and the latter half bit is '0'. That is to say, when the violation of a data '0' of the CMI rule is detected, it is a signal for outputting '1', and this signal (k) is outputted to a terminal 14 as the CMI rule violating signal of the data '0'.
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