发明名称 PEDESTAL LEVEL DETECTION CIRCUIT
摘要 PURPOSE:To detect a pedestal level at a front porch period surely and stably by detecting the fall of a horizontal synchronizing signal from a gate signal and generating a sample period signal during a prescribed front porch of a horizontal synchronizing signal after one horizontal scanning time based on said fall. CONSTITUTION:A pedestal level detection circuit 13 uses the 1st gate signal (c) to detect the fall of the horizontal synchronizing signal included in a synchronizing signal (b), the 2nd gate signal (d) is generated after a time corresponding to the width of horizontal synchronizing signal based on the fall to detect the rise of the horizontal synchronizing signal (b) and a sample period signal (e) is generated based on the rise then the horizontal synchronizing signal is detected surely and the pedestal level is sampled at the back porch of the horizontal blanking period. Further, since the digitized video signal (a) is eliminated of color burst of an LPF 117, the sample period signal (e) for a wide period including the part having color burst is generated.
申请公布号 JPS62140576(A) 申请公布日期 1987.06.24
申请号 JP19850280716 申请日期 1985.12.13
申请人 PIONEER ELECTRONIC CORP 发明人 MORIYAMA YOSHIAKI
分类号 H04N5/08;H04N5/16;H04N5/93 主分类号 H04N5/08
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