Arithmetic module for a digital computer.

摘要

The two operands for an arithmetic unit are supplied on two buses (FA and FB) for a selected pair of registers within a register file (RF 507). The register addresses (ADA and ADB) corresponding to the two buses (FA and FB) respectively are provided, in accordance with an instruction, from two input addresses (RA1 and RA2). However a swap signal (SWS) controls two multiplexers (AMUXA and AMUXB) making it possible to equate (ADA) and (ADB) with (RA2) and (RA1) respectively, instead of with (RA1) and (RA2) respectively. The swap signal may be employed in conjunction with floating point mantissa - shifting (to bring a smaller operand to the same exponent as the larger operand) so as to ensure that the unshifted mantissa is always applied to a specific one (FA) of the two buses.