| 摘要 |
PURPOSE:To simplify a circuit by making detection of the break of signal input to a transmitting part possible by only monitoring the clock frequency of a receiving part. CONSTITUTION:Input data 3 and an input clock 4 with frequency f1 are inputted to the transmitting part through an interface part 5. The peak of the clock with f1 is detected 6, compared with a reference voltage 8 by a comparator 7, and when the peak is higher than the reference value, a level L is outputted. When the peak is less than the reference value, a level H is outputted, a clamp diode 10 is switched and frequency f2 shifted from the frequency f1 is sent from an oscillator 9 to a modulating circuit 11 as a clock and transmitted through a line 12. The transmitted clock is amplified 13 in the receiving part 2 and extracted by a timing extracting circuit 14, original data are reproduced 15 on the basis of the output of the amplifier 13 and data 17 and a clock 18 are outputted. A frequency discriminating circuit 16 monitors the reproduced clock. When the clock is turned to f2, the receiving part 2 decides the clock abnormality of the transmitting part. |
