| 摘要 |
<p>A memory system is provided for charging and discharging small cells each of which has only three terminals with a charge injector controlled by a low single polarity voltage. Each of the cells includes a transistor having a current carrying electrode and a floating gate, with a control gate arranged so that a first capacitor is serially connected with a second capacitor between the current carrying electrode and the control gate, with one of the capacitors having a substantially larger capacitance than that of the other capacitor and with the other capacitor including a charge injector. The common point between the first and second capacitors is connected to the floating gate. The charge injector may include a single graded or stepped composition region or two such regions disposed near opposite faces or plates of the other capacitor, or more particularly the injector may include silicon rich regions near one or both faces of a layer of silicon dioxide.</p> |
