发明名称 CONTROL CIRCUIT FOR BUFFER MEMORY
摘要 PURPOSE:To attain a rereading action when the read information is erased by providing the directivity to the reading control of a first-in first-out memory, etc. CONSTITUTION:A negative direction reading control circuit including a reading direction line 4, selectors 8 and 9, a subtractor 16, etc. is provided to the reading control of a buffer memory 13. Thus the reading address direction is varied with designation of the line 4 carried out in a memory reading mode. This secures the memory rereading function and a decrement function of the reading address. Therefore the reading information can be transmitted again to the software by carrying out a rereading action when the reading address is erased due to a software mistake, etc.
申请公布号 JPS62139035(A) 申请公布日期 1987.06.22
申请号 JP19850278937 申请日期 1985.12.13
申请人 HITACHI LTD 发明人 OGURI YOZO;MORI MAKOTO
分类号 G06F5/06 主分类号 G06F5/06
代理机构 代理人
主权项
地址