| 摘要 |
PURPOSE:To decrease remarkably an amount of jitter by comparing rise of an input clock pulse and an output clock pulse and using an obtained phase difference so as to correct a preset value of a timer. CONSTITUTION:A timer 3 starts counting a basic clock (f) at the rise point of an input clock pulse A1 and overflows at the 10-th pulse of the clock (f). An output clock pulse B2 is started by the overflow signal and the overflow signal starts an output clock pulse B2 and sets a value set in a timer register B2 to the timer 3. The operation is repeated to start output clock pulses B3, B4. If a phase deviation takes place, a phase comparison circuit 1 detects the phase difference, a timer value correction circuit 2 sets, e.g., 5 to the timer 3 via an internal bus 5 based on the phase difference so as to start the output clock pulse B5. Thus, only the period of the pulse B5 has 11 periods and 10 periods are operated after the next pulse B6. Thus, the phase deviation is for the share of one and jitter is less.
|
