| 摘要 |
PURPOSE:To remarkably improve speed of logical simulation processing by suppressing occurrence of ineffective event out of events that occur with rise/fall of a clock signal to the utmost. CONSTITUTION:At first, at the time of initial setting, a clock signal value, for instance C0, is applied to a CLK terminal, and C0 is propagated to the part where propagation is possible. Supposing that an IN terminal is '0', C0 propagates to output of an OR gate g1. However, C0 does not propagate to output of an AND gate g2. Then, simulation is started advancing machine cycle. At this time, input value of the gate g1 remains C0, and events do not occur, and events occur only when the value of the IN terminal is changed. At this time, output value of the gate g2 can be C0 or '0'. The value of C0 is changed to '0' or '1' basing on the phase number of the clock and state of rise/fall at the time of simulation, and valuation of latch l1 is performed. |
