| 摘要 |
PURPOSE:To enable the delay time between an input terminal and an output terminal, between the input terminal and an F/F and between the F/F and the output terminal to be accurately measured by inserting a pattern to which a pattern applied to an external input terminal is inverted into the midway of a function test pattern. CONSTITUTION:When inputted with an external input terminal applied pattern, the input device 3 of a logic circuit tester 1 feeds a bit pattern to a pattern inverting device 4. The inverting device 4 generates an inverted pattern 5 to which an inputted bit pattern is inverted. A pattern editing device 6 inserts the pattern 5 into the suitable location of the pattern 2 inputted from the input device 3 and edits a test pattern 7 to be inputted to a test unit 8. The test unit 8, inputted with the pattern 7, applies it to a circuit 9 to be tested and the circuit 9 is tested by applying an input pattern and comparing output patterns. Thus, a delay time from the change in an input to the change in an output can be accurately measured. Further, the set up time of an F/F for the change in an external input and the delay time from the change in the F/F to the change in an output can be accurately measured. |
