| 摘要 |
<p>PURPOSE:To minimize the trouble and time required for the phase adjustment by providing a frequency division low speed clock generating section provided to a serial/parallel processing section to a parallel/serial processing section reduce the number of phase adjusting positions. CONSTITUTION:The parallel/serial processing section 30 is provided with the frequency division low speed clock generating section 32, to which an input high speed clock HCK is fetched via a delay line 52, the frequency division low speed clock LCK0 and shift clocks LCK1-LCKn are generated at the same time, the clock LCK0 is inputted to the serial/parallel conversion section 11 of the serial/parallel processing section 10 via a delay line 53 and the clocks LCK1-LCKn are inputted directly to the parallel/serial conversion section 31. Thus, the clock LCK0 inputted to the processing section 10 is phase-adjusted to the clock HCK so as to require only one phase adjusting position thereby facilitating the phase adjustment.</p> |
