| 摘要 |
PURPOSE:To reduce the capacitance between a gate electrode and source/drain and realize a high-speed operation of an MOS FET by making insulating films formed between the gate electrode and the source/drain thicker than a gate insulating film formed on the bottom of a groove. CONSTITUTION:After a silicon oxide film 2 is formed on a P-type semiconductor substrate 1, a resist pattern is formed and a groove 3 is formed by etching. Then, after a gate oxide film 2' is formed, tungsten films 4 and 4a are deposited and, after silicon oxide is deposited over the whole surface, the silicon oxide films 5 are left on the side walls of the groove 3 by reactive ion etching. Then polycrystalline silicon 6 doped with an impurity is deposited and, after resist 7 is applied, etched and further the tungsten films 4a are removed to leave the polycrystalline silicon layer 6' in the groove 3. Then As or P ions are implanted into the substrate 1 through the silicon oxide film 2' to form a source region 8 and a drain region 9 and the silicon oxide film 2' is removed. Further, after silicon oxide films 10, 10' and 10'' are deposited and contact holes are drilled, patterning of polycrystalline silicon wirings 11, 11' and 11'' is carried out.
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