| 摘要 |
PURPOSE:To make control of a byte alignment in each processor, unnecessary and to improve the use efficiency of a system bus, by providing an address pointer which can recognize a byte address in own word of a main storage device and a storage device, a byte counter, and a data transfer use buffer, in a system bus control part. CONSTITUTION:A system control part CSP, BSC 6 is provided with an address pointer (MSA 16, 17) 62 at the time of cycle steal of an MS 2, a cycle steal control word 65 containing an identification number (ID) of a start origin of the cycle steal, a data buffer 61 in case of a data transfer, a cycle steal byte counter 64, an F/ST 66 being a flip-flop (FF) for showing a direction of the cycle steal, an address pointer (CSA 17) 63 at the time of cycle steal of a CS 5, and an STT 67 being a flip-flop (FF) for executing a start of the cycle steal. Each register, etc., and a control flip-flop (FF) are all brought to mapping as an external register to which a firmware of a CSP 4 can execute an access.
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