发明名称 METHOD FOR TESTING INTEGRATED CIRCUIT
摘要 PURPOSE:To enable the diagnosis of trouble within a short time by collectively observing the whole, by a method wherein a potential distribution image is collectively recorded and each picture element of the image is digitalized to apply majority decision operation to the digital signal of the image along the wiring of wiring drawing data and the logical value data of the obtained signal line is compared with the expected value data of the signal line preliminarily calculated by logical simulation. CONSTITUTION:The potential distribution image of the whole of an IC chip is collectively recorded by an EB tester and each picture element thereof is subsequently digitalized to a '1' value and a '0' value. In order to correct the error of the picture element, majority decision operation is performed along the wiring of the wiring drawing data of a planning data base. That is, the interior of a wiring drawing is allowed to coincide with the '1' value or the '0' value. Further, circuit information is added to calculated the logical value table of a signal line and this table is compared with an expected value table calculated by logical simulation. When a logical value coincides with an expected value in all of compared signal lines, the absence of trouble is judged. If there is a non-coincidence signal line, trouble is present at the place relating to said signal line.
申请公布号 JPS62134577(A) 申请公布日期 1987.06.17
申请号 JP19850274969 申请日期 1985.12.09
申请人 TOSHIBA CORP 发明人 NAKAZAWA MASAHISA
分类号 G01R31/28;G01R31/302 主分类号 G01R31/28
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