| 摘要 |
PURPOSE:To enable the fine formation of a memory cell and the increase in the integration while keeping a sufficient withstand voltage by a method wherein a well isolated by an isolation layer of reverse conductivity type is provided in a semiconductor substrate, and memory cells are integrated in this well. CONSTITUTION:The P type well 12 isolated from the p type Si substrate 10 by the n type isolation layer 11 is formed in the substrate. A plurality of memory cells are formed in this well. The memory cells consist of n<+> diffused layers 13 and 14, an n<+> diffused layer 15 becoming a rewrite region joined to the layer 14, gate oxide films 161-164, a floating gate FG, and control gates CG1 and CG2. With such a construction, a fixed potential of Vc=D is given to the substrate. First, at the time of electron injection from the layer 15 to the FG of these memory cells, Vs=Va=Vb=0V is made valid, and a potential of e.g. 20V is applied to the CG1 and CG2. On the other hand, at the time of electron emission from the FG to the layer 15, the CG1 and CG2 are set at 0V, and Vs=Va= Vb=20V is made valid. At this time, breakdown does not generate. |
