发明名称 DIGITAL CHROMINANCE SIGNAL PROCESSING CIRCUIT
摘要 PURPOSE:To make proper band restriction to each of I signal and Q signal without providing a band restriction filter after demodulation and to simplify circuit configuration by connecting a BPB in 2-stage tandem. CONSTITUTION:NTSC video signals from an input terminal 1 are sampled by an A/D converter 2 and inputted to a clock generating circuit 11 as a sample string, and digital signals are inputted to a front stage BPF 3. Demodulation band of I signal is determined by the BPF 3, and a chrominance signal string 4 band restricted to wide band is applied to a rear stage BPF 5. Calculation is made to determine pass band of Q signal by the rear stage BPF 5 and a chrominance signal string band restricted to narrow band is obtained. Phase adjusted wide band chrominance signal string 6 and narrow band chrominance signal string 7 are outputted from the BPF 5, and a sample value of I component is selected from the signal string 6, and a sample value of Q component is selected from the signal string 7 by an IQ selection signal 12 from the circuit 11 in a selector circuit 8. Output of the circuit 8 is demodulated by a demodulating circuit 9, and thus, configuration of the processing circuit is made simple.
申请公布号 JPS62133882(A) 申请公布日期 1987.06.17
申请号 JP19850273221 申请日期 1985.12.06
申请人 HITACHI LTD 发明人 SAKAMOTO TOSHIYUKI;KOJIMA NOBORU;NAKAGAWA HIMIO
分类号 H04N9/64;H04N9/66 主分类号 H04N9/64
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