| 摘要 |
PURPOSE:To execute equally plural operation processings without causing the delay of a specified operation processing, by providing plural data transferring circuits, a random number generator, and a priority circuit for switching a priority between main storage reference requests in accordance with the output of the random number generator, on a main storage controlling circuit. CONSTITUTION:When a vector processor is started, and a vector processing is started, a data transferring circuit is started by a vector instruction for referring to a main storage, and by the address calculating part 1 of a data transferring circuit, an address is calculated, and stored in a register 2. A priority circuit 5 selects one of address information which is sent from each data transferring circuit through a switching circuit 3, stores it in a register 7, and simultaneously, the priority circuit 5 generates a tag for showing from which data transferring circuit the address information is selected and stores it in a register 8, and also sends a signal for signifying a fact that the address information is selected, to the address calculating part 1 through a bus 14. |
