| 摘要 |
PURPOSE:To decrease the number of elements and an operation time, and to improve the reliability by constituting the titled circuit by using almost the same module by a gate array, etc., and executing a processing in parallel even in case the number of digital signals for fetching the maximum value has increased. CONSTITUTION:In the second logic circuit 1, P0.Q0.R1=1, they are inputted to AND circuits (gate) 111-113, respectively, together with a control signal, its output is inputted to an OR circuit 101, and the maximum value bit signal Z0 outputs '1'. At the same time, this signal is inputted to an inverter 102, and '0' outputted from the inverter 102 is inputted to OR circuits 121-123, respectively, together with outputs of the AND circuits 111-113. Outputs of the OR circuits 121-123 become '0', '1', and '0' in accordance with digital signals P, Q, and R, and discriminating signals ZP, ZR, and some discriminating signal ZQ, which are outputted from AND circuits 131-133 are become '0', and '1', respectively. Accordingly, from the discriminating signal, the digital signal Q shows the maximum value, and its value becomes the maximum value signal Z, namely, 1101.
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