| 摘要 |
PURPOSE:To reduce the required time of A/D conversion and to improve the quantized accuracy by quickening a conversion clock at low-order bit decision more than that at a high-order bit decision. CONSTITUTION:A data selector 13 of a conversion clock generating circuit 1 selects a frequency division output having a low frequency at the decision of the high-order bit in an output of a frequency divider 12 and selects a frequency division output having a high frequency at the decision of a low-order bit and applies the result to a sequential comparison register 2 as a conversion clock 121. Thus, a converted analog input 502 and a reference sequential comparison analog output 401 are compared to form a comparison data 501, which is fetched in a register 2 synchronously with the clock 121 to obtain an A/D conversion output 202.
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