Frequency synthesizer having first phase locked loop frequency multiplied by near unity in second phase locked loop

摘要

A Frequency synthesis stage comprises two phase locked loops. The first (O1, D1, M, CP1, D2) divides the frequency Fo+ DELTA derived from preceding stages by N/Q, N being a variable integer, and adds to the result a standard frequency P which is in a fixed ratio with a value representative of large frequency steps so as to give an intermediate frequency FA, while the second (O2, M0, M1, CP2+L, D3) multiplies FA by NQ/r. P and Q are selected so that the product PQ is approximately equal to the mean of the limit values desired for the output frequency.