发明名称 Heterojunction FET with doubly-doped channel
摘要 There is disclosed a semiconductor device comprising at least first and second semiconductor layers positioned to form a hetero-junction therebetween, such a hetero-junction being adapted to form a channel, means for controlling carriers, and source and drain areas on opposite edges of the channel, wherein the first and second semiconductor layers formed between the source and drain regions have an area containing only 1016cm-3 or less of an impurity; the first semiconductor layer has a wider forbidden band than that of the second semiconductor layer; and further including at least one semiconductor layer having a higher activation efficiency of impurities than that of the first semiconductor layer, with such at least one semiconductor layer being located on the side of the first semiconductor layer not in contact with the second semiconductor layer. A multi-quantum well structure may be used as the higher impurity activation efficiency semiconductor layer. The electrical resistance in the semiconductor area constituting the source and drain regions can be lowered by utilizing such a higher impurity activation efficiency semiconductor layer.
申请公布号 US4673959(A) 申请公布日期 1987.06.16
申请号 US19840686661 申请日期 1984.12.27
申请人 HITACHI, LTD. 发明人 SHIRAKI, YASUHIRO;KATAYAMA, YOSHIFUMI;MURAYAMA, YOSHIMASA;MORIOKA, MAKOTO;SAWADA, YASUSHI;MISHIMA, TOMOYOSHI;KURODA, TAKAO;MARUYAMA, EIICHI
分类号 H01L29/812;H01L21/338;H01L29/205;H01L29/423;H01L29/778;(IPC1-7):H01L29/80 主分类号 H01L29/812
代理机构 代理人
主权项
地址
您可能感兴趣的专利