| 摘要 |
PURPOSE:To eliminate the variance by using two flip-flops and obtaining the synchronizing reading data which come to be a clock signal and a prescribed phase relation. CONSTITUTION:When data (b) from a PLL 1 are supplied to the terminal CK of a flip-flop 2, an input is pulled up to an electric power source voltage Vcc, therefore, a Q output comes to the high level. Since the Q output (f) comes to be the D input of a flip-flop 3, to the terminal CK, the inverting signal of a clock signal (a) is supplied, and then, the Q output comes to be the high level. Since the Q output (d) and a clock signal (a) come to be two inputs of a NAND gate 5, when the clock signal (a) occurs during the Q output period, then, the output of the NAND gate 5 comes to be the low level. An output (g) is supplied to a terminal R, therefore, the flip-flop 2 is the leading of the output (g), is reset and the output (f) comes to be the low level. As such a result, the Q output (d) comes to be also the low level in accordance with the leading of an inverting clock signal (e) and both flip-flops 2 and 3 come to be the initial condition. Thus, the variance is eliminated between data separator circuits.
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