| 摘要 |
PURPOSE:To simplify the test by providing a detection means whether the bit content of a counter is all 1 or all 0 and a means bringing all carry or borrow signal to each bit of the counter to 0 and 1. CONSTITUTION:Bits are supplied to a latch 1, a carry control MOS transistor (TR) 2 to the next stage, a precharge MOS TR 3 of a carry signal line 6, are a carry signal 4, a negative logic 6 of the carry signal line, a carry signal discharge control signal 7 and a carry signal 10 to the least significant bit and given to a half adder 5, an AND gate 8 detecting that the all bits of the counter are logical 1, a NOR gate 9 detecting that bits of the counter are logical 0. In case of latch test, all bit 1 or 0 is written in the latch 1, the test is conducted whether or not the level of the AND gate 8 or the NOR gate 9 is logical 1 and the carry signal 10 to the least significant bit is made inactive (1). Thus, the test is realized simply at a high speed. |
