| 摘要 |
PURPOSE:To retrieve the contents of memory data and to facilitate the access of related information by providing a latch circuit to hold comparing data, plural comparing circuits to divide and compare the data read from a memory cell into plural blocks, an encoder circuit to detect the result and a driving circuit to the output as an address signal. CONSTITUTION:When a memory cell array 51 is composed of 1,024 line X1,024 row by one mega bit, a line address is latched by an address buffer 54, decoded by a row decoder 52 and sent to the memory cell array 51. The 1024 outputs after selecting the memory cell array 51. The 1024 outputs after selecting the line are unified to the 16 bit output group of 64 sets through a sense amplifier part 53. Respective sets are compared in parallel by the comparing address of 15 bits and a comparator 57. The output result is encoded by an encoder 58, latched as the actual address information of 6 bits and sent to the same signal lines I9-I4 as the input address by a bus driver 56.
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