| 摘要 |
PURPOSE:To improve the information processing and transmission efficiency of a CPU, by 'off' controlling the 2nd and 3rd switches when the 1st and 4th switches are 'on' controlled and, on the contrary, 'off' controlling the 1st and 4th switches when the 2nd and 3rd switches are 'on' controlled. CONSTITUTION:A CPU 5 having a transmission data processing function, 1st and 2nd memories 9 and 10 which are provided between the CPU and a data transmission circuit 3, accessible from the CPU, and can make data transmission by means of a DMA, 1st switch 11 connected between the CPU and 1st memory 9, 2nd switch 12 connected between the 1st memory 9 and data transmission circuit 3, 3rd switch 13 connected between the CPU and 2nd memory 10, 4th switch 14 connected between the 2nd memory 10 and data transmission circuit 3, and a switch control circuit 15 which 'off' controls the 2nd and 3rd switches 12 and 13 when the 1st and 4th switches 11 and 14 are 'on' controlled and the 1st and 4th switches 11 and 14 when the 2nd and 3rd switches 12 and 13 are 'on' controlled, are provided. Therefore, the data processing and transmission efficiency of the CPU are improved.
|
