| 发明名称 |
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| 摘要 |
A MOSFET random access memory having a memory cell, an independent write-in switching means and an independent read-out control circuit. The read-out control circuit includes a first MOS transistor controlled by the data stored in the memory cell and a second MOS transistor controlled by a read-out control signal. When the data stored in the memory cell is read out, charge flow between the memory cell and the data line is prevented which results in high reliability. |
| 申请公布号 |
JPS6227477(B2) |
申请公布日期 |
1987.06.15 |
| 申请号 |
JP19810026361 |
申请日期 |
1981.02.25 |
| 申请人 |
TOKYO SHIBAURA ELECTRIC CO |
发明人 |
SASAKI ITSUO;SUZUKI HIROAKI |
| 分类号 |
G11C7/00;G11C11/41;G11C11/412;G11C11/413;G11C11/419 |
主分类号 |
G11C7/00 |
| 代理机构 |
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